The invention relates to a transistor arrangement, a method for operating a transistor arrangement as a data memory and a method for fabricating a transistor arrangement.
In view of the rapid ongoing development of computer technology, there is a need for storage media which provide ever-greater storage quantities on ever-smaller arrangements. Large quantities of data are usually stored in a large arrangement of memory cells. Memory cells used are, for example, nonvolatile memories which can store a stored information item for a long period of time without loss of information. An overview of nonvolatile memories is given by Widmann D., Mader H., Friedrich H.: “Technologie hochintegrierter Schaltungen” [Technology of Largescale Integrated Circuits], Chapter 8.4, Springer Verlag, Berlin, IBSN 3-540-59357-8 (1996), for example. Special transistors on silicon chips are usually used as nonvolatile memories.
Conventional silicon microelectronics will, however, encounter limits as miniaturization progresses further. In particular, the development of increasingly smaller and more densely arranged transistors of hundreds of millions of transistors per chip will be subject to fundamental physical problems in the next ten years. When structure dimensions fall below 80 nm, quantum effects will have a disturbing influence on the components situated on the chips, and will predominate below dimensions of about 30 nm.
Moreover, the increasing integration density of the components on the chips leads to undesirable crosstalk between the components situated on the chips and to a dramatic increase in waste heat. Therefore, increasing the storage density of transistor arrangements by means of advancing miniaturization of the transistor dimensions is a concept which will encounter physical limits in the foreseeable future.
Therefore, concepts are being pursued which seek alternatives to the progressive miniaturization of the extent of individual transistors. One concept which is being pursued in order to further increase the storage density is based on the basic idea of storing a quantity of data of more than one bit in one transistor.
Eitan B., Pavan P., Bloom I., Aloni E., Frommer A., Finzi D.: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Letters, Vol. 21, No. 11, pp. 543–545 (2000) discloses a nonvolatile memory in which a storage quantity of two bits can be stored in one transistor. The method of operation of such a nonvolatile memory is described in more detail below. FIG. 1 shows a 2-bit memory transistor 100 having a gate region 101, a source region 102, a drain region 103, a well region 104, a first electrically insulating layer 105 and a second electrically insulating layer 106. Furthermore, the 2-bit memory transistor 100 has an electrically insulating ONO layer 107 containing a first oxide layer 108 made of silicon dioxide (SiO2), a nitride layer 109 made of silicon nitride (Si3N4), and a second oxide layer 110 made of silicon dioxide (SiO2). Moreover, the 2-bit memory transistor 100 has a first memory section 111 and a second memory section 112, which are arranged at the two lateral edge sections of the nitride layer 109 in the ONO layer 107. The gate region 101 is preferably fabricated from n-doped polysilicon material. The two electrically insulating layers 105, 106 are formed from silicon dioxide (SiO2).
A quantity of data of one bit can in each case be stored in the two memory sections 111, 112, as described hereinafter. If a first, sufficiently large voltage is applied to the gate region 101 and a second, sufficiently large voltage is applied to the source region 102, this brings about tunneling of accelerated, so-called “hot”, electrons to the nitride layer 109 in the first memory section 111 of the ONO layer 107 in the vicinity of the source region 102. These electrons are then situated, in the electrically insulating nitride layer 109 in accordance with FIG. 1, immobile in the horizontal direction in the first memory section 111. The electrons cannot flow away from the first memory region 111 via the—in accordance with FIG. 1—vertically adjacent electrically insulating oxide layers 108 and 110.
The electrons injected into the ONO layer 107 from the drain region 103 via the source region 102 thus represent a fixed electrical charge. This fixed electrical charge is thus permanently localized, i.e. clearly trapped, in a region of the ONO layer 107 near the source region 102.
The application of a first, sufficiently large voltage to the gate region 101 and of a second, sufficiently large voltage to the drain region 103 analogously brings about tunneling of accelerated electrons to the nitride layer 109 in the second memory section 112 of the ONO layer 107 in the vicinity of the drain region 103. The electrons are then situated in the electrically insulating nitride layer 109 in accordance with FIG. 1 immobile in the horizontal direction in the second memory section 112 and also cannot flow away via the—in accordance with FIG. 1—vertically adjacent electrically insulating oxide layers 108 and 110. In particular, charge balancing of the electrons which are situated in the first memory section 111 and/or in the second memory section 112 is not effected along the nitride layer 109, since electrical charges cannot be transported along the electrically insulating nitride layer 109.
The presence of an electrical charge in the first memory section 111 is interpreted as a first logic value “1”, whereas an absence of an electrical charge in the first memory section 111 is interpreted as a second logic value “0”. Therefore, a quantity of data of one bit can be stored in the first memory section 111 of the ONO layer 107. The presence of an electrical charge in the second memory section 112 is interpreted as a first logic value “1”, whereas an absence of an electrical charge in the second memory section 112 is interpreted as a second logic value “0”. Therefore, a quantity of data of one bit can also be stored in the second memory section 112 of the ONO layer 107. Consequently, a storage quantity of two bits can be stored in the 2-bit memory transistor 100.
The electrons permanently localized in the two memory sections 111, 112 influence the threshold voltage of the 2-bit memory transistor 100 in a characteristic manner. The two quantities of data of in each case one bit that are stored in the memory sections 111, 112 can be read out by a first, sufficiently small voltage being applied to the source region 102 or the drain region 103, on the one hand, and a second, sufficiently small voltage being applied to the gate region 101, on the other hand. The two voltages are to be chosen to be small enough to prevent an undesirable tunneling of electrons from or to the nitride layer 109. The threshold voltage of the 2-bit memory transistor 100 is therefore clearly dependent on the presence and the absence, respectively, of free charge carriers on the nitride layer 109, since the free charge carriers have an influence on the conductivity of the arrangement and, consequently, on the current flow.
The method described in the Eitan reference described above for reading out the quantity of data stored in the memory section 111 near the source region 102 and the memory section 112 near the drain region 103, respectively, is effected in the “opposite” direction to programming. That is, to read from the memory section 111 near the source region 102, a voltage is applied to the drain region 103 and a further voltage is applied to the gate region 101. In contrast to this, in order to program the memory section 111 near the source region 102, a voltage is applied to the source region 102 and a further voltage is applied to the gate region 101. In order to read from the memory section 112 near the drain region 103, a voltage is applied to the source region 102 and a further voltage is applied to the gate region 101. The reading from the two memory sections 111, 112 in the “opposite” direction (compared with programming) enables an accelerated programming operation since smaller quantities of charge localized in the ONO layer 107 are sufficient during read-out in the “opposite” direction.
From the 2-bit memory transistors 100 described it is possible to construct arrangements having a plurality of such 2-bit memory transistors 100, such an arrangement enabling a doubled storage density in comparison with conventional memory arrangements of transistors, each of which can store a storage quantity of one bit.
However, in order to program the 2-bit memory transistors 100, it is necessary, as described above, to apply a sufficiently high voltage to the source region 102 or to the drain region 103.
If the structure sizes fall below approximately 150 nm, the high voltages required can no longer be applied to the source region 102 and to the drain region 103, respectively, without an undesirable current flow occurring between source region 102 and drain region 103. This parasitic punch-through of the space charge zone from the source region 102 to the drain region 103 adversely influences the data programmed in the two memory sections 111, 112, and the electrons permanently localized in the ONO layer 107, respectively.
A punch-through of the space charge zone between the source region 102 and the drain region 103 with the disadvantageous consequences described can be avoided by providing the horizontal extent—in accordance with FIG. 1—of the channel between the source region 102 and the drain region 103 in sufficiently large fashion. As a result, an overlap between the space charge zone formed around the source region 102 and the space charge zone formed around the drain region 103 is avoided and the two memory sections 111, 112 can then be operated with the high voltages required, without the occurrence of the disadvantageous effects described above. However, a horizontal lengthening of the channel between the source region 102 and the drain region 103, that is to say a lengthening of the ONO layer 107 in accordance with FIG. 1 in the horizontal direction, is associated with an increased area requirement of a transistor in a memory arrangement having a multiplicity of such transistors. This counteracts the aim sought, namely that of achieving the highest possible storage density, that is to say storable quantity of data per area of the arrangement.
This restriction has the effect that the 2-bit memory transistor 100 disclosed in the Eitan reference is limited to linear dimensions of not less than 150 nm. Further miniaturization is not possible by means of this arrangement. This is disadvantageous with regard to the pursued aim of providing transistors having the highest possible storage density and also having the shortest possible signal propagation times.
U.S. Pat. No. 6,087,222 A discloses a nonvolatile memory unit in which a plurality of 1-bit memory transistors are arranged one beside the other. In each case a drain electrode, a channel region, a source region, a control gate electrode and a floating gate electrode together form a 1-bit memory transistor. In this case, each 1-bit memory transistor is arranged essentially vertically with respect to the surface of the nonvolatile memory unit. The floating gate electrode consists of an electrically conductive material and serves, in each individual 1-bit memory transistor, as a data memory in which a storage quantity of one bit can be stored in each case. In order to ensure suitable electrical insulation of each control gate electrode from the remaining components of the 1-bit memory transistors, the control gate electrodes are embedded in a respective ONO layer and thus electrically decoupled from the drain electrodes, the channel regions and the floating gate electrodes.
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